| L1 |
Introduction
Course Objectives, Digital Logic, Hardware Description Languages
Logic Analyzer Demos in the Lab by TAs |
Problem Set 1 Out
Lab 1 Out |
| L2 |
Combinational Logic
Logic Gates, Boolean Algebra, Visualizations of Boolean Algebra, Hazards
Logic Analyzer Demos in the Lab by TAs (cont.) |
|
| L3 |
Introduction to Verilog® (Combinational Logic)
Logic Synthesis, The Verilog® Hardware Description Language, Combinational Logic in Verilog®, Testbenches |
|
| L4 |
Sequential Building Blocks
Preserving State with Feedback, Latches and Flip-flops, Clocks and Timing Constraints, Clock Skew
WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs |
|
| L5 |
Simple Sequential Circuits and Verilog®
Simple Counters, Verilog® Implementation of Sequential Circuits
WARP, MAX+plus II, and ModelSim Demos in the Lab by TAs (cont.) |
Problem Set 1 Due |
| L6 |
Finite-State Machines and Verilog® Implementation
Metastability and Synchronization, Mealy and Moore Formalisms, Verilog® Implementations, FSM Examples |
Problem Set 2 Out
Lab 2 Out |
| R1 |
Lab 2 Discussion and Demonstration |
Lab 1 Checkoff
Lab 1 Report Due |
| L7 |
Memories
Technologies, Types of RAM and ROM, Memory Controller Circuits, Specialty Memories, High-performance Interfaces |
|
| L8 |
Circuits for Arithmetic
Binary Addition and Subtraction, Implementation and Performance of the Full Adder, High-speed Addition, Signed Arithmetic |
|
| R2 |
Recitation |
Problem Set 2 Due |
| L9 |
Analog Building Blocks
Analog Inputs, Useful Op-amp Circuits, A/D and D/A Conversion, Useful A/D and D/A Circuits |
|
| L10 |
System Integration Issues and Major/Minor FSM
Hierarchy and Modularity, Data and Control Paths, Major and Minor FSMs, Memory Modules (RAM/ROM) in Altera, Design Tips
Lab 3 Overview |
Problem Set 3 Out |
| R3 |
Recitation |
Lab 2 Checkoff |
| L11 |
Reconfigurable Logic
Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools |
Lab 2 Report Due
Lab 3 Out |
| L12 |
Reconfigurable Logic (cont.)
Overview of Commercial Devices, Programmable Logic (PAL), FPGA Architectures, and Software Tools |
|
| R4 |
Recitation |
|
| L13 |
Video
Displays, Synchronization, Recovery of Signals, Sync Timing |
|
| L14 |
Project Kickoff
Video of Past 6.111 Projects, Project Ideas, Deadlines and Goals, Project Guidelines, Grading, Asynchronous Interfaces and Kit-to-kit Communication |
|
|
No Recitation |
Lab 3 Analog Checkoff
Problem Set 3 Due |
| L15 |
Digital Integrated Circuits and Systems
Moore's Law, VLSI Integration, Layout and Fabrication, Application-specific Circuits, Microprocessors. Behavioral and Algorithmic Transformations, Retiming, Parallelism and Pipelinling |
Special Quiz Review by TAs
Formation of Project Teams |
| R5 |
Recitation |
|
| L16 |
Power Dissipation
Heat and Battery Life Issues, Sources of Power Dissipation, Circuit and Algorithm Optimizations for Power, Voltage Scaling |
Project Abstracts Due
Lab 3 Checkoff
Lab 3 Report Due |
| L17 |
Motors and Position Determination
Servos, Position Measurement, Encoders, Motors, Windings
|
Project Proposals for Proposal Conference Due
|
| P1 |
Proposal Conference with TAs |
Lab 2 Revised Report Due (part of the MIT undergraduate communication requirement)
Project Proposals for Proposal Conference Due |
| P2 |
Block Diagram Conference with TAs |
|
| P3 |
Block Diagram Conference with TAs (cont.) |
|
| P4 |
Block Diagram Conference with TAs (cont.) |
|
| P5 |
Project Design Presentations |
Eta Kappa Nu ("HKN") Review
Customized Project Checklist Due |
| P6 |
Project Design Presentations (cont.) |
|
| P7 |
Project Design Presentations (cont.) |
|
| P8 |
Project Design Presentations (cont.) |
|
| P9 |
Implement/Debug |
|
| P10 |
Implement/Debug (cont.) |
|
| P11 |
Implement/Debug (cont.) |
|
| P12 |
Implement/Debug (cont.) |
|
| P13 |
Implement/Debug (cont.) |
|
| P14 |
Final Project Demonstrations |
Final Project Report Due (three days after session P13) |